Considering the continuously increasing processor working speed in computers, such as personal computers, workstations, and servers, it is indispensable to increase the working speed of semiconductor memories in order to prevent losses of performance. Consequently, memory modules with very fast and high density memory components, DDR-DRAMs (Double Data Rate Dynamic Random Access Memory) of generations 1, 2, and 3 have been developed in recent years, in which the working speed and structure density were continually improved.
In a conventional DIMM semiconductor memory module with DDR-DRAMs serving as semiconductor memory chips, for example, two or four ranks per semiconductor memory module are provided, where one rank each is arranged on the front and back side of the semiconductor memory module, or 2 ranks each are arranged on a same side of the semiconductor module in a stack, respectively. According to common definition, in this context “rank” denotes the number of semiconductor memory chips (DRAMs) required to cover the entire bit width of a control and address bus connecting the semiconductor memory units to a memory controller. Therefore, at a bus width of 64 bit or 72 bit including an ECC error correction component (Error Correction Code), a total of 16 (or 18 including ECC) semiconductor memory chips with 4 bit data width or 8 (or 9 including ECC) semiconductor memory chips with 8 bit data width are needed. For example, in registered DIMMs, in which, aside from the memory components, specific buffer components for signal conditioning and decoupling of a bus system provided on the system main board are provided, 4 ranks with memory units of 8 bit width each are realized. More specifically, on one x8-based DIMM with 4 ranks on the front and back side of the wiring plate two ranks each of 8 memory components each are located, which are wired together on several wiring levels by vias and signal line cable runs penetrating through the wiring board.
“Lane” designates a bus of a specific width. In the case of a DDR3 architecture, one speaks of a byte lane which then consists of 8 bits. With x4 based DRAMs, one speaks about a nibble lane. Generally, the term lane combines a group of signals which are identical among each other, which, however, differ as a group from other signals.
In a conventional memory chip topology, for example, in DDR3 DRAMs, the individual memory chips are connected by flyby topology with the memory controller. Here, the control and address signal pins of the individual memory chips are each connected in series to a flyby bus.
A major disadvantage of the flyby topology is the too narrow bandwidth for high data rates of 1.6 Gbit/s/pin, for example, and a too low structural density. An improved semiconductor memory arrangement, which allows large bandwidth and high structure density to be realized even at high data rates of at least 1.6 Gbit/s/pin, is desirable.